1. Field of the Invention
The present invention relates to a semiconductor test system for testing and evaluating functions of a semiconductor device at a high speed.
2. Description of the Prior Art
FIG. 1 is a schematic diagram showing a conventional semiconductor test system. The semiconductor test system as shown in FIG. 1 is formed by a magnetic disk unit 2 for storing a test program for performing a functional test to evaluate a semiconductor device to be tested (hereinafter referred to as "DUT") 1, a storage area 3 for storing data to be applied to respective terminals of an input terminal group 1a of the DUT 1 and expected values of outputs from an output terminal group 1b thereof in the form of truth tables respectively, a clock generator 4 for generating clock waveforms to be applied to the respective input terminals of the DUT 1 on the basis of the truth tables held in the storage area 3 and a comparator 5 for receiving output information from respective output terminals of the DUT 1 to distinguish the same by a predetermined threshold value and digitalize the same thereby to compare the digitalized output information with the expected output values included in the truth tables in the storage area 3. Symbol A depicts examples of input response series of clock waveforms supplied from the clock generator 4 to the DUT 1, and symbol B depicts examples of output waveforms from the DUT 1. The term "clock waveforms" herein used indicates those as shown by symbol A in FIG. 1, which are in binary voltage values and capable of freely setting binary changes in a certain period and applicable as a waveform group with each waveform varied in type in identical period.
Operation of the conventional semiconductor test system is now described. Information on input/output response series in/from the DUT 1, i.e., so-called test patterns, is generally retained in the magnetic disk unit 2 in the form of program files. The test patterns are stored in the storage area 3 (generally contained in the semiconductor test system) as input/output series corresponding in number to the terminals of the input and output terminal groups 1a and 1b of the DUT 1, to be easily applicable to the same. In other words, the test patterns are held in the storage area 3 in the form of a table of truth values (1, 0, X or H, L, Z etc.) which is expanded two-dimensionally with respect to the number of the terminals of the DUT 1 and time transition (depth) of test executing operation. The input series (test patterns) included in the truth tables in the storage area 3 is supplied to the respective terminals of the input terminal group la of the DUT 1 as a clock waveform group according to the truth table through the clock generator 4. The DUT 1 operates (making a functional operation) in response to the applied input series (clock waveforms) A, and then generates an output response series group B from its output terminal group 1b to supply the same to the comparator 5. The output response series group B is generally outputted in the form of the aforementioned clock waveforms.
The comparator 5 receives the output response series B to convert the same into truth values (1, 0, X or H, L, Z etc.) and compares the truth values with the expected output series included in the truth tables held in the storage area 3, thereby to generate a PASS signal when the output response series in the form of the truth values coincides with the expected output response series while generating a FAIL signal when the former does not coincide with the latter. Namely, the comparator 5 changes the output response series B received from the DUT 1 to truth values thereby to compare the same with the expected output response series held in the storage area 3 in real time.
In the aforementioned structure, however, the input and output response series held in the storage area 3 are two-dimensionally arrayed in the directions of the number of terminals and the time (depth), in order to be capable of changing them with respect to time for all of the input and output terminals of the DUT 1, and hence the truth tables are remarkably enlarged in scale with increase of the test patterns.
Also proposed in the art is a system which repeatedly rewrites truth tables in a storage area, whereas such system involves generation of dummy (waste) times associated with rewriting the test patterns and various restrictions for facilitating rewriting of the test patterns themselves.
A microcomputer or microprocessor which has a plurality of internal functions, unlike random logic circuits, operates in combination of the functions associated with each other to perform a given instructions. Therefore, when a semiconductor test system generates prescribed instructions to be executed on a microprocessor or microcomputer, one instruction to be executed may correspond to several operational cycles of the semiconductor test system, and the functional test cannot be performed at a high speed in practice. This will be described below with reference to FIG. 2.
FIG. 2 illustrates given instructions to be executed and corresponding truth tables in a conventional truth table system.
Now considered are patterns of "1" and "0" (input and expected output series) which are required for instructions to be executed "NOP", "LXI B" and "LXI H" (FIG. 2(a)). As obvious from FIG. 2, an instruction "NOP" is of one machine cycle and requires four clock states. The instructions "LXI B" and "LXI H" are of three machine cycles, both requiring ten clock states. Therefore, 24 clock states (i.e., 4+10+10) are required for executing the instructions as shown in FIG. 2(a), leading to a large scale truth table as shown in FIG. 2(b).
Further, assigned to one clock state is one test period. Therefore, if the instructions as shown in FIG. 2(a) are executed by a semiconductor test system having a maximum operation cycle of 25 nsec. (40 MHz) for one test cycle, complete execution of the instructions requires 25.times.24=600 nsec., leading to increase in execution time.
With respect to correction of the truth tables, further enlargement in scale of the truth tables involves erroneous changes of the truth values "0" and "1" as well as increased time consumption for searching the positions for their values to be changed, leading to reduced efficiency.
Now considered is the time required for forming truth tables in a semiconductor test system. Information for the truth tables is generally stored in the magnetic disk unit 2 as shown in FIG. 1, and transferred (loaded) at need to the storage area 3 for holding the truth tables. Therefore, the transfer time would increase with increase in the amount of information (i.e., truth tables) to be transferred. Further, enlargement in integration scale of the DUT 1 is followed by increase in scale of the truth tables formed in correspondence thereto, and such large-scale truth tables cannot be stored within the capacity of storage areas available at present.
In the semiconductor test system which generates clock waveforms of input/output series to/from the DUT in accordance with large-scale truth tables so as to execute a functional test of DUT, further, highly sophisticated technique is required in structure, precision etc. to cope with fast operation, leading to increase in cost.
Examples of conventional semiconductor test system in the above structure are disclosed in "Model GR18 General Purpose Complex VLSI Test System Standard Product Description and Specifications", General Semiconductor Test Inc., P/N 24180373, Rev. E, Sept. 1983 and "Sentry 50 VLSI Component Test System Product Description", Fairchild Camera and Instrument Corporation, No. 5714001, April 1983.